The present invention relates to a solid-state imaging element having a static induction transistor.
In conventional solid-state imaging devices, charge transfer elements such as CCDs (charge coupled devices), or MOS transistors are frequently used. These imaging devices, however, have various problems such as leakage of the charge during the charge transferring operation, a low light detection sensitivity and difficulty in increasing the integration density, and so on. In order to solve these problems, an imaging device having static induction transistors (SITs) have been proposed. For example, in a Japanese Patent Kokai No. 55-15,229, there is described a solid-state imaging device comprising a matrix of SITs, the sources of which are connected to row conductors, the drains to column conductors and the gates to clear conductors. In a further improved solid-state imaging device, capacitors are connected to signal storage gates of SITs and diffused layers are used as isolating gates. FIG. 1A is a perspective view showing a construction of such SIT and FIG. 1B is a circuit diagram showing a whole construction of solid-state imaging device having such SITs.
As shown in FIG. 1A, on a n.sup.+ -type silicon substrate 1 forming the sources of SITs is grown an n.sup.- -type silicon epitaxial layer 2 having an impurity concentration in the range of 10.sup.13 -10.sup.14 atoms/cm.sup.3. Hereinafter, the construction of one SIT will be explained. In the surface of said epitaxial layer 2, an n.sup.+ -type drain region 3, a p.sup.+ -type signal storage gate region 4 and a p.sup.+ -type isolating gate region 5 are provided by, for example, a thermal diffusion. The diffusion depth of the drain region 3 is smaller than those of gate regions 4 and 5. The isolating gate region 5, particularly for electrically isolating the neighboring SITs from each other can be floating or connected to a certain potential point. The signal storage gate region 4 is connected to a gate terminal 7 via a capacitor 6, which is formed by, for example, the signal storage gate region 4, an insulating film (not shown) applied thereon and a gate electrode (not shown) provided thereon. The n.sup.- -type epitaxial layer 2 forms a channel region, which has been already depleted when the element is in a steady state in which light is not incident, that is, the gate voltage is zero. Therefore, current does not flow between the source and drain regions, even if a forward bias is applied therebetween.
When the light is made incident in such a construction, hole-electron pairs are generated in the channel region or gate depletion layer. The electrons flow to the source 1 connected to earth, while the holes are stored in the signal storage gate region 4 and then charge a capacitor 6 connected to the gate region 4, so that the gate potential is increased by .DELTA.V.sub.G. Representing the capacitance of the capacitor 6 and the charges stored in the signal storage region 4 upon the incidence of light by C.sub.G and Q.sub.L, respectively, the following equation can be obtained. EQU .DELTA.V.sub.G =Q.sub.L /C.sub.G
When a gate reading pulse .phi.G is supplied to the gate terminal 7 after a certain storage time, the gate potential becomes equal to .phi.G plus .DELTA.V.sub.G. Therefore, the potential difference between the signal storage gate region 4 and the drain region 3 is lowered to reduce the depletion layer, so that a drain current corresponding to the incident light flows between the source and drain regions. The drain current is increased by the amplifying operation of SIT in accordance with .DELTA.V.sub.G multiplied by the amplification factor of the SIT. A similar operation can also be obtained when the source and drain regions of the SIT are interchanged in position.
FIG. 1B shows a circuit diagram of a solid-state imaging device, wherein such SITs are arranged in a matrix form, and FIG. 1C shows signal wave forms for explaining the operation of said imaging device. Each of the SITs 10-1, 10-2, . . . is an n-channel SIT of normally off type as described above. Output video signals are read out in accordance with light inputs in an X-Y address system. The common source of SITs, each of which forms a picture cell, is connected to earth and the drains of each row of SITs, which are arranged in an X-direction, are connected to one row line 11-1, 11-2, . . . These row lines are connected in common to a video line 13 via row selecting transistors 12-1, 12-2, . . . , respectively. The gates of each column of SITs, which are arranged in a Y-direction, are coupled to one column line 14-1, 14-2, . . . The video line 13 is connected to the positive terminal of DC supply source 16 via a load resistor 15, the negative terminal of the supply source being connected to the earth.
Now taking a case of reading the output of one SIT picture cell into consideration, if the gate reading pulse .phi.G.sub.1 is, for example, supplied to the column line 14-1 during the period of time when the transistor 12-1 connected to the first row line 11-1 is switched on by a row selection pulse .phi.S1, then the SIT 10-1 is selected and the drain current thereof flows through the video line 13 and the load resistor 15, so that an output voltage Vout appears on an output terminal 17. As described before, this drain current is a function of the gate voltage and this gate voltage is a function of the light input, so that the increment .DELTA.Vout from the output voltage at the time of no light input has a voltage corresponding to the magnitude of light input. In this case, the increment .DELTA.V.sub.G is multiplied by the amplification factor as the result of an amplifying operation of the SIT, so that the increment .DELTA.Vout of the output voltage can be large. Next, a gate reading pulse .phi.G2 is supplied to a column line 14-2 to effect the reading out of SIT 10-2. After the reading out of the first row of SITs, the transistor 12-2 is switched-on by a row selection pulse .theta.S2 and then the SITs in next row are sequentially read out.
In the SIT construction described above, however, it is necessary to make the isolating gate region 5 and the signal storage gate region 4 forming a light incident region deeper than the drain region 3 in order to be able to sufficiently open and close the channel. The depth of the drain region is usually about 0.3 .mu.m, while the depth of gate regions is usually a few microns. Therefore, this construction has a disadvantage that the sensitivity of the SIT for the shorter wave length light may be low. That is, it is apparent from FIG. 2 showing wave length dependent characteristics of light absorption coefficient of the silicon (Si) that in the range of the wave length .lambda. of visible light between 0.4 and 0.7 .mu.m, the light absorption coefficient .alpha. is equal to about 6.multidot.10.sup.4 cm.sup.-1 at .lambda.=0.4 .mu.m (violet) and is equal to about 2.multidot.10.sup.3 cm.sup.-1 at .lambda.=0.7 .mu.m (red), so that the light absorption coefficient .alpha. becomes larger as the wave length .lambda. becomes shorter. Now, when it is assumed that a light intensity at the silicon surface is I.sub.o and a light intensity at a distance of x from the silicon surface is I, the following relation is obtained. EQU I=I.sub.o e.sup.-.alpha.x
From the above equation, the distance x, at which the light intensity is reduced in the silicon by a factor of 10 (i.e. I/I.sub.o =1/10), can be obtained. That is, in the light having a longer wave length of 0.7 .mu.m, the distance x is about 12 .mu.m, while in the light having a shorter wave length of 0.4 .mu.m, the distance x is about 0.38 .mu.m. From this, it is apparent that the light having a shorter wave length is remarkably attenuated near the silicon surface. Therefore, in the SIT construction described above, the intensity of the shorter wave length component of light is considerably reduced, so that the sensitivity of the SIT for the shorter wave length component of light is low.